W.G. 3

Title: Early-Stage Timing Analysis

Working Group 3 Leader:

Prof. Tullio VARDANEGA‚ÄčProf. Tullio VARDANEGA

University of Padova, Department of Mathematics,
via Trieste 63, 35121 Padova, Italy
Telephone: +39049 827 1359 , Fax: +39049 827 1444
e-mail: tullio.vardanega <at> math.unipd.it

 

Description: WCET analysis has traditionally been used in the verification phase of a system, after all components have been built. Since redesigning a software system is very costly, designers usually choose to over-specify the hardware initially and then just verify that it is indeed sufficiently powerful. However, as systems' complexity rises, these initial safety margins can prove to be very expensive. Undertaking lightweight (but less precise) analysis in the early stages of the design process has the potential to drastically reduce total hardware costs.

A second related issue is that of portable WCET analysis. When the early-stage analysis is performed, it is clearly targeted at selecting a platform which is cost-efficient for the problem at hand. It would be highly beneficial to perform the WCET analysis in such a way that parts of the analysis can be redeployed on other hardware platforms, in order to avoid ballooning costs in the analysis.

To address this, we will study:

  • Methods to derive approximate and/or abstract timing models for source code, for higherlevel models from which code can be generated, and the associated timing analysis methods. This may be achieved by:
  • online estimation of parameters like preemption delay, WCET and cache contention; or
  • by model-checking-based approximate timing analysis.
  • Methods for fast exploration of hardware alternatives using timing estimates derived from modular, approximate, timing-composable hardware models.