Timing Analysis on Code-Level (TACLe)

Project Title: TIMING ANALYSIS ON CODE-LEVEL

Acronym: TACLe

Action: ICT COST Action IC1202, European Cooperation In Science & Research

MOU: 4133/12

CSO Aproval Date: 07/06/2012

Duration: 07/11/2012 – 06/11/2016

Embedded systems increasingly permeate our daily lives. Many of those systems are business- or safety-critical, with strict timing requirements. Code-level timing analysis (used to analyze software running on some given hardware w.r.t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organization render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques.

New principles for building "timing-compostable" embedded systems are needed in order to make timing analysis tractable in the future. This requires improved contacts within the timing analysis community, as well as with related communities dealing with other forms of analysis such as model-checking and type-inference, and with computer architectures and compilers. The goal of this COST Action is to gather these forces in order to develop industrial-strength code-level timing analysis techniques for future-generation embedded systems.

TIMING ANALYSIS ON CODE-LEVEL

 

Embedded systems

  • Software running on hardware
  • Timing predictability

Central challenge

  • Entering the multicore era
  • Industrial-strength code-level timing analysis

Means

  • Joining the European forces

 

 

Several European Institutions & Businesses are Participating:

  • WG1 Timing models for multi-cores and timing composability
  • WG2 Tooling aspects
  • WG3 Early-stage timing analysis
  • WG4 Resources other than time